摘要 |
<p>A network node includes a serial physical sublayer (PHY) chip, a parallel PHY chip, and a media access control (MAC) chip. The serial physical sublayer chip, includes a single bit transmit data input (122), a single bit receive data output (123), and serial PHY control signal input/output (I/O) lines (115). The parallel PHY chip includes a multi-bit transmit data input (132), a multi-bit receive data output (133), and parallel PHY control signal I/O lines. The MAC chip includes a multi-bit transmit data output (112), a multi-bit receive data input (113) and parallel control signal I/O lines (115). The multi-bit transmit data output (112) is connected to the multi-bit transmit data input (132). One bit of the multi-bit transmit data output (112) is connected to the single bit transmit data input (122). The multi-bit receive data input (113) is connected to the multi-bit receive data output (133). One bit of the multi-bit receive data input (113) is connected to the single bit receive data output (123). The parallel control signal I/O lines (115) are connected to the parallel PHY control signal I/O lines. A subset of the parallel control signal I/O lines (115) are connected to the serial PHY control signal I/O lines. <IMAGE></p> |