Method of making MOS transistors with a gate-side air-gap structure and an extension ultra-shallow S/D junction

摘要

This invention proposes a new process to form MOS transistor with a gate-side air-gap structure and an extension ultra-shallow S/D junction for high speed devices. After growing the thin gate oxide film on silicon substrate, a stacked-amorphous-Si (SAA) film is deposited. A thin CVD oxide film is deposited and then patterned. The top two amorphous-Si layers are etched back and then form the nitride spacers. The pad CVD oxide film is removed by diluted HF solution followed by S/D/G implant. High temperature thermal oxidation process is used to convert the bottom amorphous-Si layers outside the nitride spacers into thermal oxide and simultaneously to form shallow junction. The nitride spacers are removed and then the low energy/high dose ion implantation is performed for extension S/D junction. The bottom amorphous-Si layer is etched back and then RTP anneal in N2O or NO ambient is used to recover the etching damage to form an extension S/D junction. A thick CVD oxide film is deposited on all regions. Due to the step coverage issue, a air-gap structure would be formed at the gate side.