发明名称 |
Precharge system for a semiconductor memory device |
摘要 |
A method for precharging a bit line pair or data line pair in a semiconductor memory device includes generating a precharge pulse signal when a write enable line is deactivated at the beginning of a read cycle. The line pair is rapidly precharged by a pair of large transistors which turn on in response to the pulse signal. The pulse signal ends and turns of the transistors before a word line is enabled during the read cycle to prevent the large transistors from interfering with the bit sensing operation. A precharge circuit for precharging a bit line pair or data line pair in a semiconductor memory device includes a pulse generator having a delay circuit that determines the pulse width of a precharge pulse which is generated when a write enable line is deactivated. A write and precharge circuit includes two large transistors connected between a line pair and a power source that turn on and rapidly precharge the line pair during the precharge pulse. A third large transistor is connected between the lines of the line pair to equalize the voltages of the lines when the precharge pulse is generated.
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申请公布号 |
US5973972(A) |
申请公布日期 |
1999.10.26 |
申请号 |
US19960743021 |
申请日期 |
1996.11.04 |
申请人 |
SAMSUNG ELECTRONICS, CO., LTD. |
发明人 |
KWON, KOOK-HWAN;PARK, HEE-CHOUL |
分类号 |
G11C11/41;G11C7/10;G11C11/409;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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