发明名称 |
Method for manufacturing semiconductor devices using double-charged implantation |
摘要 |
The invention provides an isolation technique using fewer process steps and a double charged implantation step (141) for defining a well region (139) of a CMOS integrated circuit device. The invention provides steps of providing a semiconductor substrate comprising an multiple layer of films (105, 107, 109). These films include an oxide layer (105) overlying the substrate, a polysilicon layer (107) overlying the oxide layer, and a nitride layer (109) overlying the polysilicon layer. The invention also uses a step of removing a first portion of the nitride layer and a first portion of the polysilicon layer defined underlying the first portion of the nitride layer and removing a second portion of the nitride layer and a second portion of the polysilicon layer defined underlying the second portion of the nitride layer. This sequence of steps provides a partially completed semiconductor structure that defines isolation regions before forming well regions for active devices.
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申请公布号 |
US5972746(A) |
申请公布日期 |
1999.10.26 |
申请号 |
US19960727076 |
申请日期 |
1996.10.08 |
申请人 |
MOSEL VITELIC, INC. |
发明人 |
WANG, CHIH-HSIEN;CHEN, MIN-LIANG;CHANG, SAN-JUNG;PITTIKOUN, SAYSAMONE |
分类号 |
H01L21/762;H01L21/8238;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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