High frequency all digital phase-locked loop

摘要

An improved high-frequency all-digital phase-locked loop for locking a local signal in phase with an input signal is disclosed. It contains a novel digital control oscillator which includes: (a) a delay line comprising L delay gates for generating L clocks, where L is an integer and each of the delay gates has a delay time PHI ; (b) a programmable up-down N-counter, where N is an integer; (c) a multiplexer which selects one of the L clocks based on a count of the up-down N-counter programmable; and (d) an adaptive-compensative circuit for determining the value of N based on the following conditions: The adaptive-compensative circuit is implemented with a boolean encoder. This improved design allows all-digital PLL's to be constructed without a high frequency system clock, while, at the same time, maintains excellent stability and generates minimum output jitters.