| 摘要 |
The present invention includes an alignment pad set in front of a plurality of charge couple devices. The alignment pad includes a plurality of alignment patterns formed on the pad. The signals detected by the CCDs are respectively fed to a multi-processor. The multi-processor is used to determine which CCD's signal can be fed into next element. A correlated double sampling (CDS) is used to respond the detected signal and adjust dc gain of the detected signal, therefore generating adjusted image signal. A 3 to 1 R, G, B multiprocessor is connected to the CDS. An analogue to digital converter is respond the 3 to 1 R, G, B multiprocessor to convert adjusted image signal to a digital signal. Then, the image data is fed into an application specific integrated circuits (ASIC) to generate a plurality of collation datas.
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