发明名称 Editing apparatus for definition of a physical translation of logic result bit map into physical result bit map
摘要 The editing apparatus has an address parameter setting device for specifying address parameters with information relating to the setting of the content of the physical address and the logic address. An address parameter storing device stores the specified address parameters. An arrangement generating device generates an arrangement of several elements by setting several elements whose structure is a memory cell of a semiconductor memory or several adjacent memory cells, and by specifying the logic address for each of these elements. It also has an arrangement storage device for storing the generated arrangement. Independent claims also cover a method of generating the definition.
申请公布号 DE19912467(A1) 申请公布日期 1999.10.21
申请号 DE1999112467 申请日期 1999.03.19
申请人 ADVANTEST CORP., TOKIO/TOKYO 发明人 YOSHINAGA, MASAYUKI
分类号 G06F7/00;G01R31/3181;G01R31/319;G11C8/00;G11C29/44;G11C29/54;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G11C29/00;G01R31/318 主分类号 G06F7/00
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