发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To form a chip shape closer to a square even in a large-capacity memory by providing a memory cell array where a small block is laid out adjacently in the direction of the expansion of the bit line of a large block and providing a specific storage circuit at the entire memory capacity of the memory cell array. SOLUTION: When a 4M-bit DRAM is to be constituted, the size of the large block of memory cell arrays 2A-2H is constituted by the size of 3/4 of 1M bits and the small block of a memory cell array that is the size of 1/4 of 1M bits is arranged as shown by 1A-1H. More specifically, regarding the memory cell, the large blocks 2A-2H being arranged in the array of (2<m> -P)&times;2<n> and the small blocks 1A-1H being arranged in the array of P&times;2<n> are prepared, and the small blocks 1A-1H are laid out adjacently in the direction of the expansion of the bit line of the large blocks 2A-2H. The total memory capacity of the memory cell array is constituted by a storage circuit of 2<m> &times;2<n> &times;2<k> .
申请公布号 JPH11289066(A) 申请公布日期 1999.10.19
申请号 JP19980091415 申请日期 1998.04.03
申请人 TOSHIBA CORP 发明人 MIYAZAWA MASAFUMI;NOSE SHIGERU
分类号 G11C11/401;H01L21/8242;H01L27/108 主分类号 G11C11/401
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