| 摘要 |
A digital phase locked loop (PLL) comprises a phase/frequency comparator block including a comparator for comparing a reference signal with an internal clock signal obtained by dividing an output clock signal of the PLL circuit. The phase/frequency comparator supplies a two-bit signal, either one of the bits having a pulse width based on the difference between the phases or frequencies of the reference signal and internal clock signal. The two-bit signal is amplified by a CMOS latch amplifier during a sense enable cycle of the amplifier to be supplied to a digital controller, which in turn controls a voltage controlled oscillator via a D/A converter. The digital PLL circuit executes frequency acquisition and phase acquisition in a single mode to simplify the circuit configuration.
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