发明名称 Data capture circuit for asynchronous data transfer
摘要 A method and apparatus for capturing data. A first latch latches data from a data source in response to respective rising edge transitions of a first clock signal. A second latch latches data from the data source in response to respective falling edge transitions of the first clock signal. A delay circuit generates a second clock signal that lags the first clock signal by a delay period and, in response to respective transitions of the second clock signal, a multiplexer alternately selects the first latch and the second latch to output data to a storage element. A pulse strobe circuit strobes the output data into the storage element in response to the first clock signal and the second clock signal being in different states.
申请公布号 US5968180(A) 申请公布日期 1999.10.19
申请号 US19970940626 申请日期 1997.09.30
申请人 INTEL CORPORATION 发明人 BACO, JOSEPH C.
分类号 G06F5/16;(IPC1-7):G06F1/12 主分类号 G06F5/16
代理机构 代理人
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