| 摘要 |
For use in an x86-compatible processor having a translation look-aside buffer (TLB) and an associated cache with first and second ways, a hit indication circuit for, and method of, indicating when a hit has occurred in the first way of the cache and a computer system employing the system or the method. In one embodiment, the circuit includes: (1) a comparator circuit, associated with the second way of the cache, that compares addresses stored in the TLB and the second way and activates a miss signal when a cache miss is detected with respect to the second way and (2) a selection circuit, associated with the first way of the cache, that receives the miss signal from the comparator circuit and generates, in response thereto, a hit signal for the first way, the comparator and selection circuits cooperating to base a cache hit in the first way on the cache miss in the second way. |
