发明名称 CLOCK SIGNAL CONTROLLER
摘要 <p>PROBLEM TO BE SOLVED: To secure the stable operation of a system of an information processor, etc., by detecting the change of a power supply and generating a clock signal serving as a standard of operating speed of the system, based on the change detection output of the power supply. SOLUTION: If the voltage drops due to the abnormality of a main power supply 107, a comparator 112 decides that the voltage of the supply 107 which is divided between the resistances 111a and 111b is lower than the voltage of a reference voltage power supply 110. Based on the decision result of the comparator 112, a variable dividing circuit 105a adapts the larger one of two dividing ratios and divides a clock circuit 106 by the larger dividing ratio to output the divided signal 106 to a phase comparison circuit 102. The frequency of the signal 106 is equal to the frequency that is set, based on the larger dividing ratio and set lower than the system operation threshold frequency that is set when the voltage of the supply 107 has the lowest level and also set at the frequency as high as possible to secure the stable operation of a system 108.</p>
申请公布号 JPH11288325(A) 申请公布日期 1999.10.19
申请号 JP19980089734 申请日期 1998.04.02
申请人 MITSUBISHI ELECTRIC CORP 发明人 KIMURA TORU;MIZUSHIMA TATSUHIKO
分类号 G06F1/08;H03L7/18;(IPC1-7):G06F1/08 主分类号 G06F1/08
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