| 发明名称 |
Data processing apparatus registers |
| 摘要 |
A data processing system is provided including an arithmetic logic unit 20, 22, 24 receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N=3, 8</=Y-X</=16 and 3X=2Y. This arrangement is particularly suited for digital signal processing and in situations where each input operand is used a plurality of times before a new input operand is loaded in its place in a register.
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| 申请公布号 |
US5969975(A) |
申请公布日期 |
1999.10.19 |
| 申请号 |
US19960727777 |
申请日期 |
1996.10.08 |
| 申请人 |
ARM LIMITED |
发明人 |
GLASS, SIMON JAMES;JAGGAR, DAVID VIVIAN |
| 分类号 |
G06F7/499;G06F7/544;G06F7/57;G06F9/30;G06F9/38;(IPC1-7):G06F7/38 |
主分类号 |
G06F7/499 |
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