Processing instructions up to load instruction after executing sync flag monitor instruction during plural processor shared memory store/load access synchronization

摘要

An information processing system is connected to a common storage and executes programs by use of processors. This system includes a common storage; a plurality of processors, connected to the common storage. Each processor executes an instruction to store data from common storage, and an instruction to load data from the common storage into the cache storage, wherein each processor includes a communication controller for, when detecting synchronization completion information for attaining synchronization of execution of instructions among a plurality of processors, sending synchronization completion information and receiving synchronization information from another processor; an instruction executing section for detecting a specified change of the flag of a specified location in the common storage by executing a Monitor instruction included in a program in response to synchronization information from the communication controller; an execution controller to execute subsequent instructions after the Monitor instruction, exclusive of a Load instruction to load data into a cache storage, until a change of the flag is detected by the execution section, wherein the processor allows instruction for loading data from common storage into the cache storage to be executed after the flag detection, and wherein the execution controller may include an inhibit resetting circuit to issue an inhibit instruction control signal to terminate the instruction send-out inhibiting action of the instruction inhibit circuit according to input from a service processor.