| 摘要 |
PROBLEM TO BE SOLVED: To enhance an access speed by controlling the updating of a row address cache when a mistake is discriminated by the row address cache and starting row access by changing over a bank. SOLUTION: When a hit is discriminated by a row address cache(RAC) 1 and a DRAM is discriminated to be in an access operable state by an access status cache 2, column access are started and when a mistake is discriminated by the RAC 1, after the RAC 1 is updated, column access are controlled so as to be started or row access are started by changing over a bank. When access is present from a MPU to the DRAM, an access control and the generating/cotrolling of internal timings are performed by checking the RAC 1 in parallel with a decoding and based on a result in which whether an address wanted to access is cached or not and access states to be held in an access status cache(ASC) 2. |
