| 摘要 |
PURPOSE: To provide a clock recovery circuit for serial digital video which can discriminate whether an input signal is a composite video signal or a component video signal. CONSTITUTION: A clock recovery circuit 1 comprises a digital receiver 48, descrambler 52, deserializer 56 and control circuit 50. Retimed data, recovery clock 59 and carrier wave detecting signal 63 are generated from a digital input signal stream 11 to the digital receiver 48. At the descrambler 52, a descrambled data output 53 are generated by using the retimed data and reproducing clock 59. At the deserializer 56, parallel data 55 are generated from this descrambled data output 63 and a timing reference detecting signal 57 is generated from the recovery clock signal 59. The control circuit 50 is provided with an automatic fine control step and a frequency sweeping step, complements the lock of PLL 54 by performing the temperature compensation of VCO and frequency sweep while using the timing reference detecting signal 57 and the carrier wave detecting signal 63 and discriminates the video signal. |
