| 摘要 |
<p>PROBLEM TO BE SOLVED: To layout a clock net so as not to generate clock skews in a semiconductor integrated circuit. SOLUTION: By the use of flip-flop arrangement information 5a, a net list 5b and a flip-flop information 5c, and flip-flops to be connected to the same clock net are classified (steps S1-S3). When the flip-flop connected to the clock net is operated by the rise of a clock, delay calculation when the clock input of the flip-flop becomes the rising is made (steps S4 and S5). When the flip-flop connected to the cross net is operated by the falling of the clock, the delay calculation is performed (steps S4 and S6) for which the clock input of the flip-flop becomes the falling.</p> |
