SEMICONDUCTOR MEMORY HAVING MEMORY CELL ARRAY

摘要

PROBLEM TO BE SOLVED: To constitute a hierarchical bit line architecture and a word line architecture by providing plural local bit line pairs in respective rows to be connected to memory cells and connecting them to master bit lines. SOLUTION: A bit line architecture 20 has plural local bit lines and plural master bit line pairs in respective rows Cj of a memory array. Respective contacts 29 of via holes are connected to drains or sources of FET switches 27 which are connected to the local bit lines. Switching states of the respective switches 27 are controlled by corresponding control lines 28 prolonging in a column direction. Respective control lines 28 are connected to all switches 27 provided parallel in the column direction. True master bit lines MBLj are selectively connected to true local bit lines LBLj via the switches 27it . On the other hand, the MBLj are selectively connected to complementary local bit lines LBLi via switches 27ic .