发明名称 ORDERING CONTROL METHOD AND NODE
摘要 <p>PROBLEM TO BE SOLVED: To provide an ordering control mechanism which improves throughput and can perform management of ordering. SOLUTION: This concerns a distributed common memory system with plural nodes connected and has central operation processing parts A and B, memories C and D, input/output control partsαandβ, and input/output devices 1, 2, 3 and 4. The input/output control partsαandβhave memory write buffers 11 and 21 which successively store memory write outputted by the input/output devices 1, 2, 3 and 4, an ordering management circuit 4 for deciding a processed party, and a node selection table 5 having comparison data to select which node of 0 or 1 the memory write is for.</p>
申请公布号 JPH11282748(A) 申请公布日期 1999.10.15
申请号 JP19980101807 申请日期 1998.03.31
申请人 NEC KOFU LTD 发明人 TOIKAWA ATSUSHI
分类号 G06F12/06;G06F12/00;(IPC1-7):G06F12/06 主分类号 G06F12/06
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