| 摘要 |
<p>An internal clock signal generator of a synchronous memory device is provided. The internal clock signal generator includes first and second inverting portions, a delay portion, first and second switching portions, and first and second logic portions also called input and output logic circuits, respectively. The first inverting portion inverts an external clock signal. The second inverting portion inverts an output signal of the first inverting portion. The delay portion delays an output signal of the second inverting portion. The first switching portion gates an output signal of the delay portion in response to a first control signal. The second switching portion gates the output signal of the second inverting portion in response to a second control signal. The first or input logic portion performs a logic operation with respect to signals input from an external source and outputting the first and second control signals. The second or output logic portion receives a signal transmitted through a selected one of the first and second switching portions and the output signal from the first inverting portion, performs a logic operation with respect to the received signals, and outputs the internal clock signal.</p> |
