| 摘要 |
The method involves counting upwards in regulator counters (Z 11, Z 12, Z 13 ... Z 1N), each associated with one respective semiconductor (Gto 1, Gto 2, Gto 3 ... Gto N), with occurrence of a first notification pulse (RI 1, RI 2, RI 3). The count of the regulator counters is respectively loaded into a delay counter (Z 21, Z 22, Z 23 ... Z 2N), and the delay counters start to count down at occurrence of a central switch-on signal. A switch-off signal is output to the corresponding gate-controlled semiconductor, when the associated delay counter reaches zero. The method involves dividing the blocking voltage in a series circuit of gate-controlled semiconductors (Gto 1, Gto 2, Gto 3 ... Gto N), whereby a compensation of the blocking voltages is reached through displacement of switch-off times. A ramp voltage is compared with the blocking voltage of a respective semiconductor, and a notification pulse (RI 1, RI 2, RI 3) is produced at agreement of both voltages. All regulator counters (Z 11, Z 12, Z 13 ... Z 1N), each associated with one respective semiconductor, are started in an upwards count direction with the first notification pulse, whereby a regulator counter counts up, until it is stopped by a notification pulse associated with it. The count of the regulator counters is respectively loaded into a delay counter (Z 21, Z 22, Z 23 ... Z 2N), and the delay counters start to count down at occurrence of a central switch-on signal of the gate-controlled semiconductors, whereby a switch-off signal is output to the corresponding gate-controlled semiconductor, when the associated delay counter reaches zero. An Independent claim is provided for a circuit arrangement implementing the method.
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