| 摘要 |
PROBLEM TO BE SOLVED: To provide an ICE(in-circuit emulator) in which the bit number of a CPU internal signal capable to be outputted in parallel is not limited by the number of chip terminals of an ICE CPU and which does not make sampling by a trace memory difficult even when a speed of an operating frequency of the ICE CPU is increased. SOLUTION: An ICE CPU is made to build in a trace memory which traces a CPU internal signal from a CPU core 11 for processing an operation equivalent to the CPU of a debug object system as an internal trace memory 14. A bit width of the CPU internal signal read out of this internal trace memory 14 is made narrow and a bit width change circuit 15 for outputting to an ICE control circuit 4 by plural cycles is provided. |
