| 摘要 |
PROBLEM TO BE SOLVED: To prevent a fault of CPU operation at the time of a memory error. SOLUTION: The device is provided with second circuits 17, 18 and 19 for outputting a first signal when there is an error in a cache memory 14. Third circuits 21, 22 and 23, which compare an address with an error and a value of an address bus to each other and output a second signal when they match, are provided. There are provided switches 4, 5, 9 and 25, which switch so that a main memory is accessed when an address with an error of the cache memory 14 is accessed. |
