发明名称 PID filter circuit
摘要 A PID (Packet Identifier) filter circuit and an FIFO (First-in, First-out) circuit in which when there is implemented a filtering of an input packet data in answer to the PID included in the packet data, one can cope with the corresponding length of the word of die PID or position of the PID in the packet without enlarging circuit scale. There is provided, with a comparison value table for storing therein comparison values beforehand, a comparator for extracting a comparison value successively from the comparison value table, and for comparing the value of the PID in the input packet data with the comparison value taken out in every word, and a FIFO (First-in, First-out) memory for storing therein the input packet data through first-in first-out. The FIFO memory does not implement the read operation until the time when the input packet data is discriminated as being the necessary one. When the input packet data is discriminated as being the unnecessary one, it causes the input packet data to be superseded.
申请公布号 EP0949808(A2) 申请公布日期 1999.10.13
申请号 EP19990250047 申请日期 1999.02.19
申请人 NEC CORPORATION 发明人 SATO, SHINOBU
分类号 G06F5/06;H04L12/701;H04L12/801;H04L12/911;H04L13/08;H04N5/00;H04N7/08;H04N7/081 主分类号 G06F5/06
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