| 摘要 |
A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a memory, for example, a dynamic random access memory (DRAM) having a memory array which is divided into memory mats and a storage capacity of 16 mega bits or more. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
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