发明名称 Process design for wafer edge in vlsi
摘要 A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the dielectric and conducting films from damage due to wafer handling, storage, or clamping. The dielectric or conducting material is removed from the wafer edge using wafer edge exposure or edge bead rinse methods. The wafer edge exposure method is carried out at the same time the dielectric or conducting layer is being patterned.
申请公布号 US5966628(A) 申请公布日期 1999.10.12
申请号 US19980023050 申请日期 1998.02.13
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 WEI, ZIN-CHEIN;MII, YUH-JIER
分类号 H01L21/00;H01L23/31;(IPC1-7):H01L21/20 主分类号 H01L21/00
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