发明名称 |
High voltage tolerable input buffer |
摘要 |
An input buffer includes an n-channel FET having a drain region coupled to the Vcc voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. A bias circuit maintains a voltage at the source of the n-channel FET which is greater than the VSS supply voltage when a logic low voltage is applied to the input terminal.
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申请公布号 |
US5966035(A) |
申请公布日期 |
1999.10.12 |
申请号 |
US19980127701 |
申请日期 |
1998.07.31 |
申请人 |
INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
LIEN, CHUEN-DER |
分类号 |
H03K19/003;(IPC1-7):H03K5/153 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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