| 摘要 |
Disclosed is a semiconductor memory (18, 20, 100, 200) having a hierarchical bit line architecture including local bit lines (LBL1, LBL2) on a lower fabrication layer, coupled to memory cells (MC), and master bit lines (MBL) on a higher fabrication layer, each coupled to an associated sense amplifier (SAi). Local bit lines disposed in any given column are coupled to different numbers of memory cells, i.e., the local bit lines have different lengths (L1, L2) over the memory cells. A hybrid configuration is preferably employed in which one local bit line (LBL1) in a column is directly coupled via a switch (251) to an associated sense amplifier, whereas the other local bit lines in the column (LBL2-LBL4) are operatively coupled to the sense amplifier via the master bit line. The different local bit line lengths are preferably selected such that total bit line capacitance with respect to any of the memory cells is substantially equalized, thereby improving data retention time for the memory.
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