发明名称 Reduction of poly depletion in semiconductor integrated circuits
摘要 A method of forming a transistor includes the steps of forming a gate structure (56) overlying a gate oxide layer (54), wherein the gate structure (56) and gate oxide layer (54) overlie a substrate (50), thereby separating the substrate (50) into a first region (90) and a second region (92) with a channel region therebetween. The method also includes doping the gate structure (56), the first region (90) and the second region (92) and annealing the doped gate structure (56) with a laser anneal, thereby driving the dopant through a substantial depth of the gate structure (56). Lastly, a source region (94) and a drain region (96) are formed in the first region (90) and the second region (92), respectively, wherein the dopant is further driven into the gate structure (56). Consequently, the dopant is driven substantially deeper in the gate structure (56) than in the shallow source region (94) and drain region (96) junctions to allow decoupling of poly depletion from the need for shallow junctions.
申请公布号 US5966605(A) 申请公布日期 1999.10.12
申请号 US19970966308 申请日期 1997.11.07
申请人 ADVANCED MICRO DEVICES, INC. 发明人 ISHIDA, EMI
分类号 H01L21/223;H01L21/225;H01L21/268;H01L21/28;H01L21/336;(IPC1-7):H01L21/336 主分类号 H01L21/223
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