发明名称 Circuit interface synchronization using slave variable delay loop
摘要 A method and apparatus is provided for synchronizing clock signals. The method includes receiving a first reference clock signal, generating a second clock signal, modifying the second clock signal to synchronize a first feedback input clock signal with the first reference clock signal, and modifying the second clock signal to synchronize a second feedback input clock signal with a second reference clock signal. The apparatus includes a phase aligning device having a first reference clock input adapted to receive a first reference clock signal, a first feedback input, and an output. A fixed delay device is coupled between the output of the phase aligning device and the first feedback input of the phase aligning device. A slave loop is coupled to the output of the phase aligning device.
申请公布号 US5964880(A) 申请公布日期 1999.10.12
申请号 US19970987797 申请日期 1997.12.10
申请人 INTEL CORPORATION 发明人 LIU, JONATHAN H.;ALLEN, MICHAEL J.
分类号 G06F1/12;H03L7/07;H03L7/081;(IPC1-7):G06F1/12 主分类号 G06F1/12
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