发明名称 INTEGRATED CIRCUIT DESIGN METHOD AND INTEGRATED CIRCUIT DESIGN SUPPORTING DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To provide an integrated circuit design method by which the mask pattern corresponding to various design rules can be formed suitably, by enhancing the efficiency of work in a circuit design stage. SOLUTION: At the designing of a circuit element required for a mask pattern for designing integrated circuit in an integrated circuit design method, the shrunk circuit variables of the circuit element obtained by shrinking the mask pattern of the circuit element is calculated, based on the unshrunk circuit variable of the circuit element, and both the unshrunk and shrunk circuit variables are displayed on a display device 290.</p>
申请公布号 JPH11274306(A) 申请公布日期 1999.10.08
申请号 JP19980070900 申请日期 1998.03.19
申请人 ASAHI KASEI MICRO SYST CO LTD 发明人 IWAMOTO SHIGENARI
分类号 G06F17/50;G03F1/68;G03F1/70;H01L21/82;(IPC1-7):H01L21/82;G03F1/08 主分类号 G06F17/50
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