| 摘要 |
<p>PROBLEM TO BE SOLVED: To perform stable writing to a memory cell transistor. SOLUTION: A dummy cell transistor 11 is connected between a bit line 3 and writing potential Vp being in parallel with a memory cell transistor 1, the writing potential Vp is supplied to the bit line 3 via the dummy cell transistor 11, and each memory cell transistor 1 is selected. The bit line 3 is precharged up to the intermediate potential between grounding potential and the writing potential Vp , thus quickly stabilizing potential VBL of the bit line 3 at the starting point of writing operation.</p> |
