| 摘要 |
PROBLEM TO BE SOLVED: To realize the speculative execution of a non-array cache access instruction by preventing the non-array cache access instruction from being dispatched much more until head/last instructions are completed. SOLUTION: When an instruction to be loaded is dispatched, access to a cache 206 is required for two times. A logic circuit in a data unit 204 recognizes that data requiring the instruction is not arrayed, the two primitive instructions of an instruction marked as a head and an instruction marked as the last, which are required for obtaining data, are generated. The data unit 204 asserts one bit to a non-array/busy latch 208. Thus, the dispatch unit is stopped to issue the non-array instructions much more. The other instruction of an array loading instruction can be dispatched and it can be processed by a circuit 200. |
