| 摘要 |
PROBLEM TO BE SOLVED: To reduce the total scale of a matched filter circuit and also to suppress the power consumption of the circuit by preparing plural circuits which integrate the signals that are cleared, after they have been outputted once in a cycle and should secure correlation with the input signals to change their phases and hold the integrated value and sum of value to be held by themselves as the next timing and then selecting and outputting those held value in the order of phases with which the circuits secure their correlation. SOLUTION: The contents of SH(sample hold) circuits 11(1) to 11(n) of each stage are cleared once, in a cycle by a decoder 16. The signals which are inputted in each timing that is set on the basis of the clear time are defined as d1, d2,..., dn, and the signal counts which secure the correlation are defined as h1, h2,..., hn respectively. A single SH circuit has its output value S=h1d1+ fh2d2+,..., hndn after it has been cleared. Plural SH circuits where the clear timing is shifted by one to each other are prepared, and an SH circuit output value S are selectively outputted,when a cycle passed after the clearing of each SH circuit. |
