| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a buffering circuit which has one chip microcomputer of a small power consumption access to a low speed on-chip memory in one clock of CPU at higher probability and enables high fetch operation. SOLUTION: A higher-order 22 bit which has an address value adder 102 for performing memory bus width addition to a value from an address bus passed is inputted to an input port of an on-chip memory 101. A holding address of a CAM 106 (corresponding to buffer memory storage data) and a current CPU fetch address are compared by an address comparator 107 and, when they coincide, a hit signal is made low, the address adder is made to operate, fetching of the next fetch prediction data is started regarding the on-chip memory and the data are stored in a buffer block of a write mode operation, a fetch data output to the CPU is outputted from another buffer block. In the case of noncoincidence, the hit signal is high and the on-chip memory becomes an address of the CPU and output data of the memory are stored in a buffer array.</p> |
