| 摘要 |
A linear address generation apparatus is provided which adds the segment base address to the displacement provided in the instruction while the instruction is being decoded. The linear and logical address generation are combined. Whereas linear address generation may have formerly required 2-3 clock cycles, 1-2 clock cycles may be achieved using the apparatus disclosed herein. The reduced latency in generating linear addresses may lead to reduced data access latency, and further may lead to increased performance in a microprocessor employing the apparatus. Performance increases are derived from the reduced number of clock cycles required for execution of memory accesses, and due to instructions dependent upon the memory accesses receiving data more quickly. For embodiments of the microprocessor employing the x86 microprocessor architecture, the apparatus additionally detects an arithmetic carry from low order bits of the addition to higher order bits of the addition. If the microprocessor is executing in 16 bit addressing mode, the logical address is truncated to 16 bits prior to adding the address to the 32 bit segment base address. Because the additions performed in this embodiment are 32 bit additions, the truncation to 16 bits is lost. Therefore, a carry from the low order 16 bits to the high order 16 bits is detected. If the instruction is executed in 16 bit addressing mode and a carry is detected, then the microprocessor causes an exception. The instruction is then handled by a microcode unit.
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