发明名称 Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio
摘要 A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.
申请公布号 US5961649(A) 申请公布日期 1999.10.05
申请号 US19970985391 申请日期 1997.12.04
申请人 INTEL CORPORATION 发明人 KHANDEKAR, NARENDRA;GADAGKAR, ASHISH S.;KUBICK, ROBERT F.;VONBOKERN, VINCENT E.;MUTHAL, MANISH
分类号 G06F5/06;(IPC1-7):G06F1/72 主分类号 G06F5/06
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