发明名称 |
System for distributing clocks using a delay lock loop in a programmable logic circuit |
摘要 |
A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.
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申请公布号 |
US5963069(A) |
申请公布日期 |
1999.10.05 |
申请号 |
US19970971315 |
申请日期 |
1997.11.17 |
申请人 |
ALTERA CORPORATION |
发明人 |
JEFFERSON, DAVID E.;COPE, L. TODD;REDDY, SRINIVAS;CLIFF, RICHARD G. |
分类号 |
G06F1/10;H03K19/177;H03L7/081;H03L7/087;(IPC1-7):H03L7/08 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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