PLL frequency synthesizer circuit

摘要

A charge-pump circuit for use in a PLL frequency synthesizer circuit, the charge-pump circuit (25) being operated based on a first and second phase difference signals ( phi R, phi P) to be fed thereto and having an output terminal (OT4) for outputting a voltage signal (DO). The circuit includes a first analog switch (27) composed of CMOS transistors and connected between a high-potential power supply (Vcc) and the output terminal (OT4), the first analog switch being controlled based on said first phase difference signal ( phi R); and a second analog switch (31) composed of CMOS transistors and connected between the output terminal (OT4) and a low-potential power supply, the second analog switch being controlled based on said second phase difference signal ( phi P). <IMAGE>