发明名称 CMOS process for forming planarized twin wells
摘要 This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing a pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as s mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. A high temperature steam oxidation is performed to grow field oxides. The dopants are activated and driven in to form twin-wells at this step. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.
申请公布号 US5963802(A) 申请公布日期 1999.10.05
申请号 US19980014865 申请日期 1998.01.28
申请人 TEXAS INSTRUMENTS - ACER INCORPORATED 发明人 WU, SHYE-LIN
分类号 H01L21/8238;(IPC1-7):H01L21/823 主分类号 H01L21/8238
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