Multi-format reduced memory MPEG decoder with hybrid memory address generation

摘要

An address generation engine is disclosed for a digital video decoder unit coupled to memory in a digital video decoder system wherein the memory accommodates multi-format and/or reduced video data storage. The address generation engine includes a processor and address generation hardware. The processor, coupled to access encoded data to be decoded by the digital video decoder unit, has microcode for deriving from the encoded data relative location information including a vertical component and a horizontal component. The address generation hardware includes a row address register and a column address register for receiving the vertical component and horizontal component, respectively, derived by the processor. The address generation hardware is configured for generating from the vertical component and the horizontal component either a macroblock write address for writing a reconstructed macroblock of data to memory, a motion compensation read address for accessing pertinent motion vector information of the encoded data for reconstructing the macroblock, and a pan and scan offset address usable by a display unit for displaying reconstructed video data in pan and scan format.