发明名称 Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
摘要 A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.
申请公布号 US5961621(A) 申请公布日期 1999.10.05
申请号 US19970827540 申请日期 1997.03.28
申请人 INTEL CORPORATION 发明人 WU, WILLIAM S.;MACWILLIAMS, PETER D.;PAWLOWSKI, STEPHEN;JAYAKUMAR, MUTHURAJAN
分类号 G06F13/16;(IPC1-7):G06F13/00 主分类号 G06F13/16
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