发明名称 |
Full and empty flag generator for synchronous FIFOs |
摘要 |
The present invention provides an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.
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申请公布号 |
US5963056(A) |
申请公布日期 |
1999.10.05 |
申请号 |
US19960661436 |
申请日期 |
1996.06.11 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
NARAYANA, PIDUGU L.;HAWKINS, ANDREW L. |
分类号 |
G06F5/06;G06F5/10;G06F5/12;G06F5/14;(IPC1-7):H03K19/00 |
主分类号 |
G06F5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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