| 摘要 |
The memory has cells organised into groups with group transistors. The electrically erasable and programmable floating grid memory is organised into N lines of words and M asterisk K lines of bits. The memory cells places at the intersections of the word lines and bit lines each comprise a floating grid transistor (M1 - Mk). These are organised into groups. For each group there is a group transistor (TG11 - TG22) with an N-type casing connected to the selection line (SL-2, SL-2) to bias the grids of the floating grid transistors to a value for selection or non-selection of the group, depending on the read, write or erasure function of the memory. The source of the group transistor (TG11 - TG22) is connected to the grids of all the floating grid transistors of the group with which it is associated.
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