| 摘要 |
A sample hold circuit has a first sample hold circuit and a second sample hold circuit, which are of the same in circuit configuration, each having a clamping circuit at an input stage of the sample hold circuit and a sample-holding circuit at the next stage, and the first sample hold circuit and the second sample hold circuit receiving commonly at least a clamping reference voltage, a clamping control signal for the clamping circuit and a sampling control signal for the sample-holding circuit. An output of a CCD image sensor is inputted to only one of the first sample hold circuit and the second sample hold circuit, whereby the output signals from the first sample hold circuit and the second sample hold circuit are outputted in a differential mode. It is possible to reduce low frequency 1/f noise and reset pulse noise in the image signal produced by the CCD image sensor by inputting the output signals from the first and second sample hold circuits to a differential circuit. |
