| 摘要 |
The technique allows the different transistor types to be manufactured in tandem. The procedure provides for fabrication of a JFET transistor within an integrated circuit containing complementary MOS transistors. The JFET transistor is formed in a casing (3) of N-type material in a P-type substrate (1). It includes the stages of forming a region (6-2) which is a P-type channel at the same time as the weakly doped drain and source regions of the MOS transistors with a P-type channel. It then includes forming an N-type grid region (8-2) at the same time as weakly doped drain and source regions for the N-type channel MOS transistors. Finally, P-type drain and source regions (10-2) are formed at the same time as the strongly doped drain and source regions for the MOS transistors having a P-type channel. |
