发明名称 Asynchronous FIFO memory
摘要 The memory (1) stores data with a write clock rate and reads out data in the same sequence with a read clock rate. It has a data input and data output, a number (N) of memories (RAM A,B,C), a status register (10) to hold status data to indicate the status of each of the memories. A cyclic write memory pointer (6) identifies the memory to be written to, according to the status data held in the status register. A cyclic read memory pointer (8) identifies the memory to be read from according to the status data held in the status register. The input data are cyclically written to memory under control of the write memory pointer. In similar cyclic succession under control of the cyclic read memory pointer, the data are read out again. The write memory pointer and read memory pointer are controlled by the status register which contains information about the condition of the single memories.
申请公布号 DE19812917(A1) 申请公布日期 1999.09.30
申请号 DE19981012917 申请日期 1998.03.24
申请人 SIEMENS AG 发明人 MARIGGIS, AFHANASE
分类号 G06F5/10;G06F5/14;(IPC1-7):G06F12/00;G11C5/00 主分类号 G06F5/10
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