| 摘要 |
A method for making reduced-size FLASH EEPROM memory circuits, and to the resulting memory circuit. An FET integrated circuit having two different gate oxide thicknesses deposited at a single step, where a portion of the thickness of the thicker oxide is formed, that oxide is removed from the area of the chip to have the thinner oxide, then the rest of the thicker oxide is grown during the time that the thinner oxide is grown on the area of the chip to have the thinner oxide. Layers for the floating gate stacks are deposited. Trenches are etched in a first, and then a second perpendicular direction, and the perpendicular sides of the stacks are covered with vertical-plane nitride layers in two separate operations. Tungsten word lines and bit contacts are deposited. Aluminum-copper lines are deposited on the bit lines.
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