| 摘要 |
A field strength detection circuit e.g. for mobile phones, has an extremely low possibility of self-oscillation and a reduced power dissipation, and is capable of being integrated at a larger scale. This circuit is comprised of first, second, and third transistors Q1-Q3 whose emitters are coupled together, which are driven by a common constant current sink 14 connected to the coupled emitters of the transistors Q1-Q3. First and second loads 11, 12 are connected to the collectors of the first two transistors Q1, Q2 and a third load 20 is connected to a collector of the third transistor Q3. The third load includes an integrator 21. An input voltage is applied across bases of the first and second transistors Q1-Q2 while a reference voltage 13 is applied to a base of the third transistor Q3. A rectified output current with respect to the input voltage is generated at the collector/drain of the third transistor and integrated by the integrator in the third load, thereby producing an output proportional to the level of the input voltage. The bipolar resistors shown may be replaced by FET's with source and drain replacing collector and emitter respectively. As an alternative the integrator may be connected to the loads 11 and 12 and several stages may be cascaded. |
