| 摘要 |
<p>A data latch circuit includes a differential amplifier (18) for detecting a potential difference between a pair of signal transmission lines (13, 14) for transmitting a pair of complementary signals, a latch timing signal generator (20) for generating a latch timing signal based on the detection by the differential amplifier (18), and a latch section (11, 12, 16, 17) for responding to the latch timing signal to latch the complementary signals transferred thereto. A reliable and high-speed signal transmission can be achieved even in a semiconductor device having a large chip size.</p> |
